In a semiconductor device using MOSFET (metal-oxide semiconductor field-effect transistor), accompanied with high performance and integration, thinning of the gate insulator film constituting the MOSFET has been advanced. For instance, to improve electric current driving capability in a MOSFET of gate length of 100 nm or less, film thickness thereof is required to be 1.5 nm or less in accordance with a scaling law when a silicon oxidation film is used as the gate insulator film. On the other hand, when such a ultra-thin silicon oxidation film is used as the gate insulator film, tunnel electric current generated with sandwiching the gate insulator film in applying a gate bias can not be ignored to source/drain electric current. To suppress such increase of the tunnel electric current has been a major issue in achieving high performance and low electric power consumption in the MOSFET.
In addition, in these years, development of extra-low-power-consumption device has been required with a focus on mobile use. In these semiconductor devices for mobile use, individual element itself is designed in a device scale in which the film thickness of the gate insulator film can be formed larger compared with the semiconductor device for high performance and integration. In order to achieve extra-low power consumption as a whole, however, it is required to drastically reduce unnecessary leak electric current such as the tunnel electric current in application of the gate bias compared with conventional devices using silicon oxidation film as the gate insulator film.
Thus, some techniques have been developed for thinning in effective (electrical) film thickness of the gate insulator film and simultaneously suppressing the tunnel electric current within allowable values on the device design both of a high-performance element and a low-power-consumption element.
One of the techniques is a method constituted of; adding nitrogen into a silicon oxidation film to form the gate insulator film having an increased dielectric constant compared with a pure silicon oxidation film, and thereby reducing effective film thickness of the gate insulator film without physically thinning the film thickness. Further in recent years, there has been carried out, instead of the silicon oxidation film, an approach to use as insulating material for the gate insulator film, insulative metal oxide thin film with the dielectric constant of 10 or more or an insulative silicate thin film formed with composite material of these insulative metal oxide material and silicon. Rare-earth element oxide such as Al2O3, ZrO2, HfO2, and Y2O3, lanthanoid rare-earth element oxide such as La2O3, or silicate thin film thereof are under consideration.
In addition, in case of using insulating material with the high-dielectric constant as the gate insulator film, improvement of electric properties of boundary face, namely, interface between the gate insulator film and a silicon substrate is a significant development subject.
As a solution, there is proposed layer structure constituted of an insulating film of insulating material with high dielectric constant (defined herein as a high-dielectric insulating material film), an interface oxide film and the silicon substrate by inserting an interface layer based the silicon oxidation film between the high-dielectric insulating material film and the silicon substrate. Following methods are listed as a method of forming the layer structure provided with this interface oxide film, for instance, a method of previously forming an oxide film layer on a silicon substrate surface as a base oxide film prior to film forming of the high-dielectric insulating material film, or a method of directly forming the high-dielectric insulating material film on the silicon substrate surface, thereafter subjecting the silicon substrate to heat treatment, and thereby growing a thermally-oxidized film layer on an interface.
While, as mentioned above, regarding the gate insulator film constituting individual element, various properties are required depending on the use and further when constituting an integrated circuit using a plurality of elements a technique is required to form on the same substrate, for instance, many kinds of purposive transistors different from each other in the respective element constitutions.
Specifically, there are cases of forming on the same substrate a transistor for high speed operation and a transistor of low-power-consumption type and of forming a transistor constituting an internal circuit and a transistor of input/output portion. In these cases, different kinds of transistors are desirably designed for different element structures in which thickness of the gate insulator film is appropriately selected depending on respective uses. Further regarding a tunnel insulating film used in a flash memory etc. an insulating film different from the gate insulator film of normal MOSFET is used, thereby optimization thereof is required to be performed.
When preparing an integrated circuit using a plurality of different kinds of elements, a technique is required to form on the same substrate plural kinds of insulating films different in effective (electric) film thickness depending on each kind of element. This preparing technique is called multi-oxide process. Now, development of the technique is pressing need, and some of the techniques have been proposed before.
A first technique of the multi-oxide process already proposed is a process of preparing a plural kind of insulating films different in film thickness by sequentially repeating the following steps of; patterning a silicon oxidation film formed on a silicon substrate surface through a resist mask and hydrofluoric acid solution treatment, providing an opening of partially stripped off silicon oxidation film, thereafter forming desired insulating film (silicon oxidation film) at the opening portion.
A second technique of the multi-oxide process already proposed is a process of forming plural kinds of insulating films different in the film thickness by performing ion implantation into a specific portion of a silicon substrate surface, and changing (speeding up) oxidation rate in the ion implantation region compared with the other region. These processes are now under discussion.
In the techniques of the multi-oxide process already proposed above, debate is proceeding with a central focus on a technique of selectively changing film thickness of the silicon oxidation film itself. However, following problems exist in the process. For instance, in the technique of sequentially repeating steps of partially exfoliating of the silicon oxidation film through the resist mask and selective wet-etching and thereafter forming the silicon oxidation film again at the opening, entire steps become complicated as the kinds of the prepared silicon oxidation film different in the film thickness increase, and further exposure on a wafer surface after exfoliating of the silicon oxidation film becomes a problem.
A cleaning step of removing the contamination on the wafer surface in the silicon oxidation film exfoliating portion (device region) comprises the steps of exfoliating the resist mask with chemical, and thereafter cleaning an entire wafer surface with mixture of ammonia and hydrogen peroxide solution and mixture of sulfuric acid and hydrogen peroxide solution, and then there is formed a thin oxide film (chemical oxide film) on the silicon surface. The oxide film remaining after this cleaning step has variation in film thickness and is inferior in insulation properties and crude in film quality. Therefore, when forming a thinner gate oxide film, the step of forming the gate oxide film is performed after previously exfoliating with the hydrofluoric acid solution.
However, this step of exfoliating chemical oxide film (etching removal) is carried out after removing the resist mask covering a thick silicon oxidation film surface, and therefore a problem that loss in film thickness is slightly caused in the thick silicon oxidation film region arises.
In order to deal with the loss nitriding treatment or cladding different kind of insulating film is performed on the thick silicon oxidation film surface that reduces etching rate than that of the chemical oxide film formed in the cleaning step of the above exposure removal. A process utilizing the difference in etching rate is proposed to suppress the loss on the thick silicon oxidation film surface which is caused through exfoliating of the chemical oxide film.
The detail of the process is, for instance, disclosed in Japanese laid open patent number 2001-196464.
On the other hand a step of recovering damages arising from ion irradiation is indispensable for controlling oxidization rate. For instance in case of adding a step accompanied by heat treatment, undesired affection may arise to other steps. Further it is pointed out from a practical standpoint that there exists constraint in the aspect of productivity and cost accompanied by the step of the selective ion irradiation.
As described above, in order to realize optimization of individual element performance, specifically high performance and low electric power consumption it is necessary to use high-dielectric insulating material film and to employ a multi-oxide process corresponding to it, instead of silicon oxide.
In case of utilizing high-dielectric insulating material film it is already proposed as element constitution that insulating films different from each other are employed between a high speed operation element and an element with the type of low electric power consumption or between an element constituting internal circuit and an element at input/output portion. Specifically, combination of silicon oxidation film or silicon oxynitride film and metallic oxidation film with high-dielectric insulation can be thought as the element constitution. As for the corresponding multi-oxide process, the step of the above high-dielectric insulating material film is focused on a deposition technique onto silicon substrate surface.
Accordingly, it is difficult in general to apply the technique utilized in controlling oxidation rate of silicon substrate by ion implantation.
Therefore, when utilizing the deposition technique onto silicon substrate surface in the step of forming the high-dielectric insulating material film, a method can be thought as a basic example of the corresponding multi-oxide process, in which partially forming an opening portion by the use of mask such as resist, in addition, oxidization or oxidizing and nitriding of the opening region, and depositing high-dielectric insulating material film are sequentially repeated.
Then, as in the case of the multi-oxide process utilizing silicon oxidation films it is supposed that there arise deterioration of uniformity in film thickness and contamination of silicon substrate surface exposed on the opening portion, etc. accompanied by forming the opening. Particularly in case of utilizing metal oxide films with high-dielectric insulation, it is concerned that adhesion of metal element to silicon substrate surface arising from the removal (etching) step becomes a new factor of contamination, because the silicon substrate surface is exposed to the opening portion.
Accordingly, it is desired to propose a new element constitution in semiconductor device and a new process suitable for a multi-oxide process corresponding to a multi-oxide structure which enables to avoid new factors of contamination supposed to arise in utilizing those high-dielectric insulating material films, and which utilizes high-dielectric insulating material films formed by the use of deposition techniques.